PIC18LF8585T-I/PT【PDF 26/424 页】IC PIC MCU FLASH 24KX16 80TQFP

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2004 Microchip Technology Inc.

DS30491C-page 119

PIC18F6585/8585/6680/8680

REGISTER 9-9:

PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3

R/W-0

IRXIE

WAKIE

ERRIE

TXB2IE/

TXBnIE

TXB1IE(1) TXB0IE(1)

RXB1IE/

RXBnIE

RXB0IE/

FIFOWMIE

bit 7

bit 0

bit 7

IRXIE: CAN Invalid Received Message Interrupt Enable bit

= Enable invalid message received interrupt

= Disable invalid message received interrupt

bit 6

WAKIE: CAN bus Activity Wake-up Interrupt Enable bit

= Enable bus activity wake-up interrupt

= Disable bus activity wake-up interrupt

bit 5

ERRIE: CAN bus Error Interrupt Enable bit

= Enable CAN bus error interrupt

= Disable CAN bus error interrupt

bit 4

When CAN is in Mode 0:

TXB2IE: CAN Transmit Buffer 2 Interrupt Enable bit

= Enable Transmit Buffer 2 interrupt

= Disable Transmit Buffer 2 interrupt

When CAN is in Mode 1 or 2:

TXBnIE: CAN Transmit Buffer Interrupts Enable bit

= Enable transmit buffer interrupt; individual interrupt is enabled by TXBIE and BIE0

= Disable all transmit buffer interrupts

bit 3

TXB1IE: CAN Transmit Buffer 1 Interrupt Enable bit(1)

= Enable Transmit Buffer 1 interrupt

= Disable Transmit Buffer 1 interrupt

bit 2

TXB0IE: CAN Transmit Buffer 0 Interrupt Enable bit(1)

= Enable Transmit Buffer 0 interrupt

= Disable Transmit Buffer 0 interrupt

bit 1

When CAN is in Mode 0:

RXB1IE: CAN Receive Buffer 1 Interrupt Enable bit

= Enable Receive Buffer 1 interrupt

= Disable Receive Buffer 1 interrupt

When CAN is in Mode 1 or 2:

RXBnIE: CAN Receive Buffer Interrupts Enable bit

= Enable receive buffer interrupt; individual interrupt is enabled by BIE0

= Disable all receive buffer interrupts

bit 0

When CAN is in Mode 0:

RXB0IE: CAN Receive Buffer 0 Interrupt Enable bit

= Enable Receive Buffer 0 interrupt

= Disable Receive Buffer 0 interrupt

When CAN is in Mode 1:

Unimplemented: Read as ‘0’

When CAN is in Mode 2:

FIFOWMIE: FIFO Watermark Interrupt Enable bit

= Enable FIFO watermark interrupt

= Disable FIFO watermark interrupt

Note 1: In CAN Mode 1 and 2, this bit is forced to ‘0’.

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

- n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

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